The present invention relates to a code error detection and correction technique, and more particularly to method and apparatus for detecting and correcting code error of a digital audio signal suitable to microwave PCM broadcasting.
As an example of a code comprising a first frame having a plurality of words and a plurality of parity words for correcting a code error and a second frame having words of a plurality of different first frames distributed therein and having a plurality of parity words for use in detecting code errors in the second frame, a code is known which comprises a first frame having 32 data words and two parity words derived from a linearly independent generating polynomial and a second frame having 32 interleaved data words derived by interleaving words of a plurality of first frames and a 18-bit CRC (cyclic redundancy check) code for detecting an error in the second frame. The formats of the second and first frames of the code are shown in FIGS. 1 and 2, respectively.
In FIG. 1, numeral 1 denotes 32 data words distributed in the second frame derived by interleaving the data words of a plurality of first frames, numeral 2 denotes two distributed (interleaved) parity words for correcting an error word in the first frame, and numeral 3 denotes the 18-bit CRC code for detecting an error in the second frame. In FIG. 2, numeral 4 denotes the 32 data words of the first frame and numeral 5 denotes the two parity words for correcting an error in the first frame.
By using the two sets of parity words and a CRC code, all errors in 18-bit burst length of the data words 1 of the second frame and in the CRC code 3 can be detected by the CRC code 3, and up to two errors existing in the first frame after de-interleaving comprising the 32 data words 4 and the linearly independent two parity words 5 can be corrected.
A decoding scheme of the code is described below. Bit errors in the second frame are detected by the CRC code 3, and if at least one bit is in error, erasure flags indicating that there is a possibility of the occurrence of an error word are added to all of the data words 1 in the second frame. Then, the words of a plurality of second frames are reconfigured to the first frame by the deinterleaving, and the linearly independent two parity words 5 in the reconfigured first frame are used to correct up to two errors.
However, in the correction by the parity words 5 of the first frame, the correction is not possible if the erasure flags have been added to three or more words of the words 4 and 5 of the first frame. In a digital audio system, an error concealment by a mean value interpolation or a previous value holding is effected.
However, in the error detection by the uncorrected CRC code, if at least one bit in the second frame is in error, the erasure bits are added to all of the words 1 and 2 in the second frame even if all other bits are correct. As a result, a probability of the inclusion of the words with the erasure flags in the deinterleaved first frame is high and hence a probability of the correction by the mean value interpolation or the previous value holding is high.
Further, in the correction by the linearly independent parity words 5 of the first frame, a circuit scale of a correction circuit is large because of a correction algorithm. Thus, in order to avoid this problem a correction operation circuit having a read-only memory (ROM) may be attempted. However, even with such a circuit, the circuit scale is still large.
An error correction method for video tape PCM recording and reproducing which has a high error correction capability for a burst error and a random error and a reduced probability for failure of error detection and incorrect error correction is disclosed in UK patent application GB No. 2,079,994A based on the Japanese patent application Nos. 55-84424, 55-84428 and 55-84427 (filed on June 20, 1980). However, in this method, the amount of serially transmitted data (1 word=8 bits) per frames and the number of parity bits are large, an encoding/decoding circuit (error detection and correction circuit) is complex and the circuit scale is large.
In many cases, the error detection/correction codes are added to the digital audio signal in order to detect and correct the code errors. The Reed-Solomon code is suitable for the error detection/correction code from a standpoint of a code efficiency.
A prior art code error detection/correction system which uses the Reed-Solomon code is now explained. FIG. 3 shows a block diagram thereof. In the illustrated example, one symbol or word comprises 6 bits, and 3-symbol parity symbols are added to every 49 data symbols (one frame) to configure the Reed-Solomon code. A parity check matrix H is represented by ##EQU1## where .alpha. is a root of a generating polynomial of the Reed-Solomon code.
In FIG. 3, numeral 11 denotes a data/parity symbol input terminal, numeral 12 denotes a first syndrome operation circuit, numeral 13 denotes a second syndrome operation circuit, numeral 14 denotes a third syndrome operation circuit, numeral 15 denotes a syndrome check circuit, numeral 16 denotes an R-S latch, numeral 17 denotes a coincidence circuit, numeral 18 denotes a counter, numeral 19 denotes an error address latch, numeral 20 denotes an error pattern latch, numeral 21 denotes an error pattern output terminal, numeral 22 denotes an error address output terminal and numeral 23 denotes an error flag output terminal.
Symbols applied to the data/parity symbol input terminal 11 are sequentially supplied to the first to third syndrome operation circuits 12-14. When 49 data symbols and 3 parity symbols have been applied, the first to third syndrome operation circuits 12-14 produce first to third syndromes, respectively. The syndrome check circuit 15 checks to see if all of the first to third syndromes are "0", and if at least one syndrome is not "0", the R-S latch 16 is set to set an error flag in order to indicate the detection of the code error. On the other hand, if all of the three syndromes are "0", it indicates no code error and the error flag is not set.
After the error detection, the error correction operation is started in accordance with the following algorithm. If the error is only in the i-th symbol having an error pattern e.sub.i, the first to third syndromes S.sub.1, S.sub.2 and S.sub.3 are EQU S.sub.1 =e.sub.i EQU S.sub.2 =.alpha..sup.52-i e.sub.i EQU S.sub.3 =.alpha..sup.104-2i e.sub.i
S.sub.2 and S.sub.3 are multiplied by .alpha..sup.-52 and .alpha..sup.-104, respectively, and then multiplied by .alpha. and .alpha..sup.2, respectively, by i times. Thus, we get .alpha..sup.i-52 S.sub.2 =e.sub.i and .alpha..sup.2i-104 S.sub.3 =e.sub.i. They correspond to the value of S.sub.1 or the error pattern. Thus, by checking the coincidence with S.sub.1 while counting the number of times of the multiplication of .alpha. and .alpha..sup.2 to .alpha..sup.-52 S.sub.2 and .alpha..sup.-104 S.sub.3, respectively, the count i at which the coincidence occurs is an address of the error symbol, and the error pattern S.sub.1 or e.sub.i is determined. In this manner, the error is corrected.
In the circuit of FIG. 3, after the error detection, the second and third syndrome operation circuits 13 and 14 multiply .alpha..sup.-52 and .alpha..sup.-104 to the contents S.sub.2 and S.sub.3, respectively. Then, the counter 18 is cleared and the second and third syndrome operation circuits 13 and 14 multiply .alpha. and .alpha..sup.2 to the contents .alpha..sup.-52 S.sub.2 and .alpha..sup.-104 S.sub.3, respectively. The counter 18 is counted up for every multiplication and the coincidence of the contents of the first to third syndrome operation circuits 12 to 14 is checked by the coincidence circuit 17. When the coincidence circuit 17 detects the coincidence of the contents of the first to third syndrome operation circuits 12 to 14, it produces a coincidence pulse. As a result, the R-S latch 16 is reset and the error address latch 19 latches the content of the counter 18 while the error pattern latch 20 latches the content of the first syndrome operation circuit 12. Thus, if an incorrectable error in which two or more symbols are in error is detected, an error flag is produced at the error flag output terminal 23, and if a correctable one-symbol error is detected, an error pattern is produced at the error pattern output terminal 21 and an error address is produced at the error address output terminal 22, and the error is corrected. At this time, the error flag is not produced at the error flag output terminal 23.
In the Reed-Solomon code having a code distance of four explained above, all of up to three symbol errors can be detected for the error detection only, but miscorrection (or incorrect correction) occurs for the three symbol errors if one symbol error correction is carried out. In the digital audio reproducing system, the errors are detected and corrected, and if data is incorrectable, the error concealment by the previous value holding or the mean value interpolation is effected by the error flag added to the data. However, since no error flag is added to the data not detected or incorrectly corrected, the error concealment is not effected and a click noise is generated.
In the prior art code error detection/correction apparatus described above, when a signal state is degraded and a code error rate increases and a probability of three symbol errors increases, a probability of the miscorrection increases. On the other hand, if the error correction operation is inhibited and only the error detection operation is carried out in order to prevent the miscorrection, the error correction ability of the Reed-Solomon code is not effectively utilized for a case where the code error rate is low and the error is correctable.